In conventional DRAM semiconductor memory systems and memory chips, data, command and address signals to/from a memory controller and/or to/from other semiconductor memory chips are not transmitted in the form of signal frames and not serially, but in parallel. This parallel transmission, for example of write data, commands and addresses, is effected via separate data, command and address signal buses from the memory controller to one or more DRAM memory chips.
In future semiconductor memory systems, e.g., DRAM memory systems and memory chips, the data, command, and address signals will be transmitted with a very high transmission rate as serial signal streams in the form of signal frames corresponding to a predetermined protocol.
In such progressive semiconductor memories, there is, between their memory core and a transmitting/receiving interface device, a frame decoder which is arranged for decoding signal frames received from a receiving interface device and for the further transmission of data and commands to the memory core. Since write data units belonging to one another can be contained not only in a single signal frame but also in a number of successively transmitted signal frames depending on the protocol, which also applies to command units belonging to one another such a semiconductor memory chip must have a temporary storage device, which is connected to the frame decoder and the memory core and which is arranged for temporarily storing a number of data and/or command units decoded by the frame decoder, and which provides the flexibility, which is absolutely necessary, in the transfer process of the write data units and/or command units to the memory core in such a progressive semiconductor memory chip.